DYNAPSE

pyaer.dynapse.DYNAPSE(device_id=1, bus_number_restrict=0, dev_address_restrict=0, serial_number='')

DYNAPSE.

Arguments

device_id: int
a unique ID to identify the device from others. Will be used as the source for EventPackets being generate from its data.
default is 1
bus_number_restrict: int
restrict the search for viable devices to only this USB bus number.
default is 0
dev_address_restrict: int
restrict the search for viable devices to only this USB device address.
default is 0
serial_number: str
restrict the search for viable devices to only devices which do possess the given Serial Number in their USB SerialNumber descriptor.
default is ""

obtain_device_info

obtain_device_info(handle)

Obtain DYNAPSE info.

This function collects the following information from the device:

Deveice ID
Device serial number
Device USB bus number
Device USB device address
Device string
Logic version
If the device is a master camera
Chip ID
If the device has AER statistics
If the device has MUX statistics

Arguments

handle: caerDeviceHandle
a valid device handle that can be used with the other libcaer functions, or None on error.

open

open(device_id=1, bus_number_restrict=0, dev_address_restrict=0, serial_number='')

Open device.

Arguments

device_id: int
a unique ID to identify the device from others. Will be used as the source for EventPackets being generate from its data.
default is 1
bus_number_restrict: int
restrict the search for viable devices to only this USB bus number.
default is 0
dev_address_restrict: int
restrict the search for viable devices to only this USB device address.
default is 0
serial_number: str
restrict the search for viable devices to only devices which do possess the given Serial Number in their USB SerialNumber descriptor.
default is ""

set_bias_from_json

set_bias_from_json(file_path, fpga_bias=True, clear_sram=False, setup_sram=False, scope='all', verbose=False)

Set bias from loading JSON configuration file.

Arguments

file_path: str
absolute path of the JSON bias file.
fpga_bias: bool
Set FPGA biases if True, False otherwise,
default is True
clear_sram: bool
Clear SRAM if True, False otherwise, Default is False
setup_sram: bool Setup SRAM if True, False otherwise,
default is False
scope: str, dict
a dictionary that describe the bias setting profile, set everything if the argument is "all" Here is a basic template for scope description

scope = {
    0: [0, 1, 2, 3],
    1: [0, 1, 2, 3],
    2: [0, 1, 2, 3],
    3: [0, 1, 2, 3],
    }

clear_sram

clear_sram()

Clear SRAM for all chips.

setup_sram

setup_sram()

Setup SRAM for all chips.

set_chip_bias

set_chip_bias(bias_obj, chip_id, core_ids=[0, 1, 2, 3], clear_sram=False, setup_sram=False)

Set bias for a single chip.

Arguments

bias_obj: dict
a dictionary that consists of all 4 core's biases
chip_id: int
chip id is between 0-3
core_ids: list
list of core ids from 0 to 3, each element is a string, the default is [0, 1, 2, 3]
e.g.,
- [0, 3]: set core 0 and core 3
- [2]: set core 2
- []: do not set core level biases
clear_sram: bool
Clear SRAM if True, False otherwise,
default is False
setup_sram: bool
Setup SRAM if True, False otherwise,
default is False

set_bias

set_bias(bias_obj, fpga_bias=True, clear_sram=False, setup_sram=False, scope='all')

Set bias from bias dictionary.

You don't have to turn on the clear_sram and setup_sram for reloading biases.

Arguments

bias_obj: dict
dictionary that contains DYNAPSE biases.
fpga_bias: bool
Set FPGA biases if True, False otherwise,
default is True
clear_sram: bool
Clear SRAM if True, False otherwise,
default is False
setup_sram: bool
Setup SRAM if True, False otherwise,
default is False
scope: str, dict
a dictionary that describe the bias setting profile, set everything if the argument is "all" Here is a basic template for scope description

scope = {
    0: [0, 1, 2, 3],
    1: [0, 1, 2, 3],
    2: [0, 1, 2, 3],
    3: [0, 1, 2, 3],
    }

Returns

flag: bool
True if set successful, False otherwise.

set_fpga_bias

set_fpga_bias(bias_obj)

Set FPGA biases.

Arguments

bias_obj: dict
dictionary that contains FPGA biases for the device.

set_activity_bias

set_activity_bias(bias_obj, chip_id, core_ids=[0, 1, 2, 3])

Set biases for each chip.

Arguments

bias_obj: dict
dictionary that contains activity biases for target chip.
chip_id: uint8_t
one of DYNAPSE_CONFIG_DYNAPSE_U0, DYNAPSE_CONFIG_DYNAPSE_U1, DYNAPSE_CONFIG_DYNAPSE_U2, DYNAPSE_CONFIG_DYNAPSE_U3
core_ids: list
list of core ids from 0 to 3, each element is a int, the default is [0, 1, 2, 3]
e.g.,
- [0, 3]: set core 0 and core 3
- [2]: set core 2
- []: do not set core level biases

get_cf_bias

get_cf_bias(param_addr, param)

Get coarse-fine bias.

Note: biases for neurons currently cannot be recalled.

Arguments

param_addr: int
a parameter address, to select a specific parameter to update from this particular configuration module. Only positive numbers (including zero) are allowed.
param: int or bool
a configuration parameter's new value.

Returns

coarse_value: uint
coarse value
fine_value: uint
fine value

get_fpga_bias

get_fpga_bias()

Get bias settings from FPGA.

Returns

bias_obj: dict dictionary that contains DYNAPSE current bias settings.

save_fpga_bias_to_json

save_fpga_bias_to_json(file_path)

Save FPGA bias to JSON.

Only the bias from FPGA can be retrieved.

Arguments

file_path: str
the absolute path to the destiation.

Returns

flag: bool
returns True if success in writing, False otherwise.

start_data_stream

start_data_stream(send_default_config=True)

Start streaming data.

Arguments

send_default_config: bool
send default config to the device before starting the data streaming.
default is True

core_xy_to_neuron_id

core_xy_to_neuron_id(core_id, column_x, row_y)

Map core ID and column/row address to the correct chip global neuron address.

Arguments

core_id: uint8
the chip's core ID, range [0, 3].
column_x: uint8
the neuron's column address, range [0, 15].
row_y: uint8
the neuron's row address, range [0, 15].

Returns

neuron_id: uint16
chip global neuron address

core_id_to_neuron_id

core_id_to_neuron_id(core_id, neuron_id_core)

Map core ID and per-core neuron address to the correct chip global neuron address.

Arguments

core_id: uint8
the chip's core ID, range [0, 3].
neuron_id_core: uint8
the neuron's address within this core, range [0, 255].

Returns

neuron_id: uint16
chip global neuron address.

write_poisson_spikerate

write_poisson_spikerate(neuron_id, rate)

Specifies the poisson spike generator's spike rate.

Arguments

neuron_id: uint16
The target neuron of the poisson spike train, range [0,1023].
rate: float
The rate in Hz of the spike train, this will be quantized to the nearest supported level, range [0, 4300].

Returns

flag: bool
True if success, False otherwise

write_sram_N

write_sram_N(neuron_id, sram_id, virtual_core_id, sx, dx, sy, dy, destination_core)

Write one of the 4 SRAMs of a single neuron.

Writing the SRAM means writing the destination address of where the spikes will be routed to. This works on the on-chip SRAM!

Arguments

neuron_id: uint16
the neuron to program, range [0, 1023]
sram_id: uint8
SRAM address, range [0, 3]
virtual_core_id: utin8
fake source core ID, set it to this value instead of the actual source core ID, range [0, 3].
sx: bool
X direction, can be one of: [DYNAPSE_CONFIG_SRAM_DIRECTION_X_EAST, DYNAPSE_CONFIG_SRAM_DIRECTION_X_WEST].
dx: uint8
X delta, number of chips to jumps before reaching destination, range is [0, 3]
sy: bool
Y direction, can be one of: [DYNAPSE_CONFIG_SRAM_DIRECTION_Y_NORTH, DYNAPSE_CONFIG_SRAM_DIRECTION_Y_SOUTH].
dy: uint8
number of chips to jumps before reaching destination, range is [0, 3]
destination_core: uint8
spike destination core, uses one-hot coding for the 4 cores [C3, C2, C1, C0] -> [0, 0, 0, 0] (0 decimal) no core, [1, 1, 1, 1] (15 decimal) all cores

Returns

flag: bool
True if success, False otherwise

write_cam

write_cam(input_neuron_id, neuron_id, cam_id, synapse_type)

Write a single CAM.

To specify which spikes are allowed as input into a neuron.

Arguments

input_neuron_id: uint16
the neuron address that should be let in as input to this neuron, range [0, 1023].
neuron_id: uint16
the neuron address whose CAM should be programmed, range [0,1023].
cam_id: uint8
CAM address (synapse), each neuron has 64, range [0,63].
synapse_type: uint8
one of the four possible synaptic weights:

[DYNAPSE_CONFIG_CAMTYPE_F_EXC,
 DYNAPSE_CONFIG_CAMTYPE_S_EXC,
 DYNAPSE_CONFIG_CAMTYPE_F_INH,
 DYNAPSE_CONFIG_CAMTYPE_S_INH].

Returns

flag: bool
True if success, False otherwise

get_event

get_event()

Get Event.

Returns

spike_events: numpy.ndarray
a 2-D array that has the shape of (N, 4) where N is the number of spike events in the packet. Each row of the array has a single spike event. The first value is the timestamp of the event. The second value is the neuron ID. The third value is the chip ID. The last value is the source core ID.
num_spike_events: int
the number of the spike events.

Bias Example

{
    "mux_timestamp_reset": false,
    "mux_force_chip_bias_enable": false,
    "mux_drop_aer_on_transfer_stall": false,
    "aer_ack_delay": 0,
    "aer_ack_extension": 0,
    "aer_wait_on_transfer_stall": false,
    "aer_external_aer_control": false,
    "chip_req_delay": 30,
    "chip_req_extension": 30,
    "usb_early_packet_delay": 8,

    "c0_if_buf_p_coarse": 3,
    "c0_if_buf_p_fine": 80,
    "c0_if_rfr_n_coarse": 3,
    "c0_if_rfr_n_fine": 3,
    "c0_if_nmda_n_coarse": 7,
    "c0_if_nmda_n_fine": 0,
    "c0_if_dc_p_coarse": 7,
    "c0_if_dc_p_fine": 30,
    "c0_if_tau1_coarse": 7,
    "c0_if_tau1_fine": 5,
    "c0_if_tau2_coarse": 6,
    "c0_if_tau2_fine": 100,
    "c0_if_thr_n_coarse": 4,
    "c0_if_thr_n_fine": 120,
    "c0_if_ahw_p_coarse": 7,
    "c0_if_ahw_p_fine": 0,
    "c0_if_ahtau_n_coarse": 7,
    "c0_if_ahtau_n_fine": 35,
    "c0_if_ahthr_n_coarse": 7,
    "c0_if_ahthr_n_fine": 0,
    "c0_if_casc_n_coarse": 7,
    "c0_if_casc_n_fine": 0,
    "c0_pulse_pwlk_p_coarse": 3,
    "c0_pulse_pwlk_p_fine": 106,
    "c0_ps_weight_inh_s_n_coarse": 7,
    "c0_ps_weight_inh_s_n_fine": 0,
    "c0_ps_weight_inh_f_n_coarse": 7,
    "c0_ps_weight_inh_f_n_fine": 0,
    "c0_ps_weight_exc_s_n_coarse": 7,
    "c0_ps_weight_exc_s_n_fine": 0,
    "c0_ps_weight_exc_f_n_coarse": 7,
    "c0_ps_weight_exc_f_n_fine": 0,
    "c0_npdpii_tau_s_p_coarse": 7,
    "c0_npdpii_tau_s_p_fine": 40,
    "c0_npdpii_tau_f_p_coarse": 7,
    "c0_npdpii_tau_f_p_fine": 0,
    "c0_npdpii_thr_s_p_coarse": 7,
    "c0_npdpii_thr_s_p_fine": 40,
    "c0_npdpii_thr_f_p_coarse": 7,
    "c0_npdpii_thr_f_p_fine": 0,
    "c0_npdpie_tau_s_p_coarse": 7,
    "c0_npdpie_tau_s_p_fine": 0,
    "c0_npdpie_tau_f_p_coarse": 7,
    "c0_npdpie_tau_f_p_fine": 40,
    "c0_npdpie_thr_s_p_coarse": 7,
    "c0_npdpie_thr_s_p_fine": 0,
    "c0_npdpie_thr_f_p_coarse": 7,
    "c0_npdpie_thr_f_p_fine": 0,
    "c0_r2r_p_coarse": 4,
    "c0_r2r_p_fine": 85,

    "c1_if_buf_p_coarse": 3,
    "c1_if_buf_p_fine": 80,
    "c1_if_rfr_n_coarse": 3,
    "c1_if_rfr_n_fine": 3,
    "c1_if_nmda_n_coarse": 7,
    "c1_if_nmda_n_fine": 0,
    "c1_if_dc_p_coarse": 7,
    "c1_if_dc_p_fine": 30,
    "c1_if_tau1_coarse": 0,
    "c1_if_tau1_fine": 5,
    "c1_if_tau2_coarse": 6,
    "c1_if_tau2_fine": 100,
    "c1_if_thr_n_coarse": 4,
    "c1_if_thr_n_fine": 120,
    "c1_if_ahw_p_coarse": 7,
    "c1_if_ahw_p_fine": 0,
    "c1_if_ahtau_n_coarse": 7,
    "c1_if_ahtau_n_fine": 35,
    "c1_if_ahthr_n_coarse": 7,
    "c1_if_ahthr_n_fine": 0,
    "c1_if_casc_n_coarse": 7,
    "c1_if_casc_n_fine": 0,
    "c1_pulse_pwlk_p_coarse": 3,
    "c1_pulse_pwlk_p_fine": 106,
    "c1_ps_weight_inh_s_n_coarse": 7,
    "c1_ps_weight_inh_s_n_fine": 0,
    "c1_ps_weight_inh_f_n_coarse": 7,
    "c1_ps_weight_inh_f_n_fine": 0,
    "c1_ps_weight_exc_s_n_coarse": 7,
    "c1_ps_weight_exc_s_n_fine": 0,
    "c1_ps_weight_exc_f_n_coarse": 7,
    "c1_ps_weight_exc_f_n_fine": 0,
    "c1_npdpii_tau_s_p_coarse": 7,
    "c1_npdpii_tau_s_p_fine": 40,
    "c1_npdpii_tau_f_p_coarse": 7,
    "c1_npdpii_tau_f_p_fine": 0,
    "c1_npdpii_thr_s_p_coarse": 7,
    "c1_npdpii_thr_s_p_fine": 40,
    "c1_npdpii_thr_f_p_coarse": 7,
    "c1_npdpii_thr_f_p_fine": 0,
    "c1_npdpie_tau_s_p_coarse": 7,
    "c1_npdpie_tau_s_p_fine": 0,
    "c1_npdpie_tau_f_p_coarse": 7,
    "c1_npdpie_tau_f_p_fine": 40,
    "c1_npdpie_thr_s_p_coarse": 7,
    "c1_npdpie_thr_s_p_fine": 0,
    "c1_npdpie_thr_f_p_coarse": 7,
    "c1_npdpie_thr_f_p_fine": 0,
    "c1_r2r_p_coarse": 4,
    "c1_r2r_p_fine": 85,

    "c2_if_buf_p_coarse": 3,
    "c2_if_buf_p_fine": 80,
    "c2_if_rfr_n_coarse": 3,
    "c2_if_rfr_n_fine": 3,
    "c2_if_nmda_n_coarse": 7,
    "c2_if_nmda_n_fine": 0,
    "c2_if_dc_p_coarse": 7,
    "c2_if_dc_p_fine": 30,
    "c2_if_tau1_coarse": 0,
    "c2_if_tau1_fine": 5,
    "c2_if_tau2_coarse": 6,
    "c2_if_tau2_fine": 100,
    "c2_if_thr_n_coarse": 4,
    "c2_if_thr_n_fine": 120,
    "c2_if_ahw_p_coarse": 7,
    "c2_if_ahw_p_fine": 0,
    "c2_if_ahtau_n_coarse": 7,
    "c2_if_ahtau_n_fine": 35,
    "c2_if_ahthr_n_coarse": 7,
    "c2_if_ahthr_n_fine": 0,
    "c2_if_casc_n_coarse": 7,
    "c2_if_casc_n_fine": 0,
    "c2_pulse_pwlk_p_coarse": 3,
    "c2_pulse_pwlk_p_fine": 106,
    "c2_ps_weight_inh_s_n_coarse": 7,
    "c2_ps_weight_inh_s_n_fine": 0,
    "c2_ps_weight_inh_f_n_coarse": 7,
    "c2_ps_weight_inh_f_n_fine": 0,
    "c2_ps_weight_exc_s_n_coarse": 7,
    "c2_ps_weight_exc_s_n_fine": 0,
    "c2_ps_weight_exc_f_n_coarse": 7,
    "c2_ps_weight_exc_f_n_fine": 0,
    "c2_npdpii_tau_s_p_coarse": 7,
    "c2_npdpii_tau_s_p_fine": 40,
    "c2_npdpii_tau_f_p_coarse": 7,
    "c2_npdpii_tau_f_p_fine": 0,
    "c2_npdpii_thr_s_p_coarse": 7,
    "c2_npdpii_thr_s_p_fine": 40,
    "c2_npdpii_thr_f_p_coarse": 7,
    "c2_npdpii_thr_f_p_fine": 0,
    "c2_npdpie_tau_s_p_coarse": 7,
    "c2_npdpie_tau_s_p_fine": 0,
    "c2_npdpie_tau_f_p_coarse": 7,
    "c2_npdpie_tau_f_p_fine": 40,
    "c2_npdpie_thr_s_p_coarse": 7,
    "c2_npdpie_thr_s_p_fine": 0,
    "c2_npdpie_thr_f_p_coarse": 7,
    "c2_npdpie_thr_f_p_fine": 0,
    "c2_r2r_p_coarse": 4,
    "c2_r2r_p_fine": 85,

    "c3_if_buf_p_coarse": 3,
    "c3_if_buf_p_fine": 80,
    "c3_if_rfr_n_coarse": 3,
    "c3_if_rfr_n_fine": 3,
    "c3_if_nmda_n_coarse": 7,
    "c3_if_nmda_n_fine": 0,
    "c3_if_dc_p_coarse": 7,
    "c3_if_dc_p_fine": 30,
    "c3_if_tau1_coarse": 0,
    "c3_if_tau1_fine": 5,
    "c3_if_tau2_coarse": 6,
    "c3_if_tau2_fine": 100,
    "c3_if_thr_n_coarse": 4,
    "c3_if_thr_n_fine": 120,
    "c3_if_ahw_p_coarse": 7,
    "c3_if_ahw_p_fine": 0,
    "c3_if_ahtau_n_coarse": 7,
    "c3_if_ahtau_n_fine": 35,
    "c3_if_ahthr_n_coarse": 7,
    "c3_if_ahthr_n_fine": 0,
    "c3_if_casc_n_coarse": 7,
    "c3_if_casc_n_fine": 0,
    "c3_pulse_pwlk_p_coarse": 3,
    "c3_pulse_pwlk_p_fine": 106,
    "c3_ps_weight_inh_s_n_coarse": 7,
    "c3_ps_weight_inh_s_n_fine": 0,
    "c3_ps_weight_inh_f_n_coarse": 7,
    "c3_ps_weight_inh_f_n_fine": 0,
    "c3_ps_weight_exc_s_n_coarse": 7,
    "c3_ps_weight_exc_s_n_fine": 0,
    "c3_ps_weight_exc_f_n_coarse": 7,
    "c3_ps_weight_exc_f_n_fine": 0,
    "c3_npdpii_tau_s_p_coarse": 7,
    "c3_npdpii_tau_s_p_fine": 40,
    "c3_npdpii_tau_f_p_coarse": 7,
    "c3_npdpii_tau_f_p_fine": 0,
    "c3_npdpii_thr_s_p_coarse": 7,
    "c3_npdpii_thr_s_p_fine": 40,
    "c3_npdpii_thr_f_p_coarse": 7,
    "c3_npdpii_thr_f_p_fine": 0,
    "c3_npdpie_tau_s_p_coarse": 7,
    "c3_npdpie_tau_s_p_fine": 0,
    "c3_npdpie_tau_f_p_coarse": 7,
    "c3_npdpie_tau_f_p_fine": 40,
    "c3_npdpie_thr_s_p_coarse": 7,
    "c3_npdpie_thr_s_p_fine": 0,
    "c3_npdpie_thr_f_p_coarse": 7,
    "c3_npdpie_thr_f_p_fine": 0,
    "c3_r2r_p_coarse": 4,
    "c3_r2r_p_fine": 85,

    "d_buffer_coarse": 1,
    "d_buffer_fine": 2,
    "d_ssp_coarse": 0,
    "d_ssp_fine": 7,
    "d_ssn_coarse": 0,
    "d_ssn_fine": 15,
    "u_buffer_coarse": 1,
    "u_buffer_fine": 2,
    "u_ssp_coarse": 0,
    "u_ssp_fine": 7,
    "u_ssn_coarse": 0,
    "u_ssn_fine": 15
}